Big data has emerged as a strategic property of nations and organizations. There are driving needs to generate values from big data. However, the sheer volume of big data requires significant storage capacity, transmission bandwidth, computations, and power consumption. It is expected that systems with unprecedented scales can resolve the problems caused by varieties of big data with daunting volumes. Nevertheless, without big data benchmarks, it is very difficult for big data owners to make choice on which system is best for meeting with their specific requirements. They also face challenges on how to optimize the systems and their solutions for specific or even comprehensive workloads. Meanwhile, researchers are also working on innovative data management systems, hardware architectures, operating systems, and programming systems to improve performance in dealing with big data.

This workshop, the eighth its series, focuses on architecture and system support for big data systems, aiming at bringing researchers and practitioners from data management, architecture, and systems research communities together to discuss the research issues at the intersection of these areas.

Call for Papers


The workshop seeks papers that address hot topic issues in benchmarking, designing and optimizing big data systems. Specific topics of interest include but are not limited to:

  • Big data workload characterization and benchmarking
  • Performance analysis of big data systems
  • Workload-optimized big data systems
  • Innovative prototypes of big data infrastructures
  • Emerging hardware technologies in big data systems
  • Operating systems support for big data systems
  • Interactions among architecture, systems and data management
  • Hardware and software co-design for big data
  • Practice report of evaluating and optimizing large-scale big data systems

Papers should present original research. As big data spans many disciplines, papers should provide sufficient background material to make them accessible to the broader community.

Download CFP

Paper Submissions

Papers must be submitted in PDF, and be no more than 8 pages in standard two-column SIGPLAN conference format including figures and tables but not including references. Shorter submissions are encouraged. The submissions will be judged based on the merit of the ideas rather than the length. Submissions must be made through the on-line submission site.

Submission site:


Important Dates

Papers due                                February 16,  2017
Notification of acceptance      February 28,   2017
Workshop Session                     April 9,        2017



Opening remark



Keynote I: Scalable In-memory Computing: A Perspective from Systems Software [pdf]

Speaker: Prof. Haibo Chen, Shanghai Jiao Tong University

Abstract: In-memory computing promises 1000X faster data access speed, which brings opportunities to boost transaction processing speed into a higher level. In this talk, I will describe our recent research efforts in providing speedy in-memory transactions at the scale of millions of transactions per second. Specifically, I will present how we leverage advanced hardware features like HTM, RDMA to provide both better single-node and distributed in-memory transactions and query processing, how operating systems and processor architecture could be refined to further ease and improve in-memory transaction processing, as well as how concurrency control protocol can be adapted accordingly to fit our need.

Bio: Haibo Chen is a Professor at the School of Software, Shanghai Jiao Tong University, where he currently leads the Institute of Parallel and Distributed Systems (IPADS) ( Haibo’s main research interests are building scalable and dependable systems software, by leveraging cross-layering approaches spanning computer hardware system virtualization and operating systems. He received best paper awards from ICPP, APSys and EuroSys, a best paper nominee from HPCA, the Young Computer Scientist Award from China Computer Federation, the distinguished Ph.D thesis award from China Ministry of Education and National Youth Top-notch Talent Support Program of China. He also received fault research award/fellowship from NetApp, Google, IBM and MSRA. He is currently the steering committee co-chair of ACM APSys, the general co-chair of SOSP 2017 and serves on program committees of SOSP 2017, ASPLOS 2017, Oakland 2017, EuroSys 2017 and FAST 2017 as well as the editorial board of ACM Transactions on Storage.



Talk I: Big Data Dwarfs: Methodology, Dwarf Library and Simulation Benchmarks [pdf]

Speaker: Ms. Wanling Gao, ICT, CAS

Abstract: The complexity and diversity of big data analytics workloads make understanding them difficult and challenging. Identifying abstractions of frequently-appearing operations is an important step toward fully understanding big data analytics workloads, which we call big data dwarfs. In this talk, we present our recent work on big data dwarf identification, and provide a dwarf library consisting of frequently-appearing operations. Based on that, we implement dwarf benchmarks for micro-architectural simulation, which have been evaluated on X86 and ARM processors.

Bio: Wangling Gao is a Ph.D candidate in computer science at the Institute of Computing Technology, Chinese Academy of Sciences and University of Chinese Academy of Sciences. Her research interests focus on big data benchmark and big data analytics. She received her B.S. degree in 2012 from Huazhong University of Science and Technology.


Tea Break



Invited Talk II: CCTLib Tutorial Pinpointing Software Inefficiencies with Fine-grained Program Monitoring [pdf]

Speaker: Prof. Xu Liu, College of William and Mary

Abstract: Complex code bases with several layers of abstractions have abundant inefficiencies that affect the execution time. Inefficiencies arise from myriad causes such as developer’s inattention to performance, inappropriate choice of abstractions, algorithms and data structures, ineffective or detrimental compiler optimizations, among others. Not all inefficiencies are easy to detect or eliminate with compiler optimization; compilers have inherent limitations of static analysis and optimization scope. Classical “hotspot” performance analysis tools are also incapable of identifying many kinds of software inefficiencies. Microscopic observation of whole executions at instruction- and operand-level granularity breaks down abstractions and helps recognize inefficiencies that masquerade in complex programs. In this talk, we will introduce CCTLib, a library for efficiently collecting execution-wide call paths and associating execution metrics with call paths in any Pin tool. CCTLib is simple to use and effective in improving a Pin-tool’s diagnostic capabilities. We introduce simple, yet effective, CCTLib APIs that offer rich calling context capabilities for Pin tools. We will introduce advanced CCTlib features for attributing every memory access to the corresponding data object in the program. We will introduce CCTLib internals for advanced users. We will show example Pin tools for detecting certain classes of software inefficiencies such as dead stores and redundant computations. Using CCTLib for these clients, we will show how one can pinpoint software inefficiencies in large, complex code bases and show how one can gain a superior understanding of execution profiles. Using CCTLib’s pinpointing capabilities we show how one can tune their code to eliminate inefficiencies and obtain significant performance improvements.

Bio: Xu Liu is an assistant professor in the Department of Computer Science at College of William and Mary. He obtained his Ph.D. from Rice University in 2014. His research interests are parallel computing, compilers, and performance analysis. Prof. Liu has been working on a few open-source performance tools, which are world-widely used at universities, DOE national laboratories, and in industry. Prof. Liu received HPC fellowships from NAG, Schlumberger, and BP while a Ph.D. candidate at Rice University. After joining W&M, Prof. Liu received Best Paper Award at SC’15.


Regular Paper I: Benchmarking Kudu Distributed Storage Engine on High-Performance Interconnects and Storage Devices

Authors: Nusrat Sharmin Islam, Md. Wasi-ur-Rahman, Xiaoyi Lu, Dhabaleswar K. (DK) Panda
(The Ohio State University)

Abstract: During the past several years, Hadoop MapReduce and Spark have proven to be the two most popular Big Data processing frameworks and Hadoop Distributed File System (HDFS) is the underlying file system for both of them. But data in HDFS is static; it does not allow any update operations on the stored data. Consequently, in order to accelerate Online Analytical Processing (OLAP) workloads, novel storage engines such as Kudu has emerged. All these Big Data processing frameworks along with the underlying storage engines are being increasingly used on High-Performance Com- puting (HPC) systems. It is, therefore, critical to understand the interaction of Kudu for fast analytics on rapidly changing data. Moreover, as the amount of data increases, the performance of Kudu becomes bounded by both network as well as storage perfor- mances. In this paper, we evaluate Kudu operations over different interconnects and storage devices on HPC platforms and observe that the performance of Kudu improves by up to 21% when moved to IP-over-InfiniBand (IPoIB) 100Gbps from 40GigE Ethernet. Sim- ilarly, while the underlying storage device is switched from hard disk to SSD, Kudu operations show a speed up of up to 29%. To the best of our knowledge, this is the first study to analyze the performance of Kudu over high-performance interconnects and storage devices.


Lunch Break



Invited Talk III: A Case for Labeled von Neumann Architecture

Speaker: Prof. Yungang Bao, ICT, CAS

Abstract: Datacenters are far from efficient in reducing tail latency and guaranteeing user experience, although there have been lots of efforts on software stack optimization. To address this challenge, the co-design of hardware and software is needed. In this talk, we propose Labeled von Neumann Architecture (LvNA), which enables a new hardware/software interface by introducing a labeling mechanism to convey software’s semantic information such as quality-of-service and security to the underlying hardware. LvNA is able to correlate labels with various entities (e.g., virtual machine, process and thread), propagate labels in the whole machine and program differentiated services rules based on labels. We argue that LvNA is promising to be a fundamental hardware support for future datacenters.

Bio: Yungang Bao is a Professor of Institute of Computing Technology (ICT), CAS and serves as the executive director of Center of Advanced Computer Systems of ICT. His research interests include computer architecture and operating systems. He invented the Hybrid Memory Trace Tool (HMTT) [SIGMETRICS’08] which is deployed in companies such as Huawei and its traces have been freely used by the community. His work on Partition-Based DMA Cache [HPCA’10] is absorbed and implemented in Intel’s Data Direct I/O (DDIO) technology. He was in charge of PARSEC 3.0 during his postdoc at Princeton University and introduced network applications and SPLASH-2X. He proposed Labeled von Neumann Architecture (LvNA) to address the inefficiency and uncertainty issue in datacneters and has built a proof-of-concept prototype — Programmable Architecture for Resourcing-on-Demand (PARD) [ASPLOS’15], which has been influencing Huawei’s CPU products. He was the winner of CCF-Intel Young Faculty Researcher Program of the year for 2013 and serves on program committees of ASPLOS, SC, ICS, IISWC etc. He was invited to participate in the Dagstuhl Seminar on Rack-scale Computing in 2015 and be a keynote speaker at China National Computer Congress (CNCC) in 2016 with about 5,000 audiences.



Invited Talk IV: CEDAR: A Distributed Database for Scalable OLTP

Speaker: Prof. Weining Qian, East China Normal University

Abstract: Many traditional applications in areas such as finance, telecommunications, transportation, retail, and etc, are using the Internet to widen user base and promote service quality. This kind of offline-to-online transformation brings heavy burden to the backend of mission-critical applications, mainly transaction and payment systems. Some sales promotion activities even create phenomenal heavy workloads. Recent developments have shown that this phenomenon will become increasingly common. Existing database management systems suffer the problem of poor scaling-out capability, while so-called NoSQL systems lack of the full OLTP support. We started our research and development on a scalable transaction processing system from year 2013. In this talk, I will share our research result on the system architecture, techniques of transaction compilation and optimization, commit log synchronization and optimization, and indexing and query processing. I will also introduce the applications of the system, and discuss the challenges we are facing in these applications.

Bio: Weining Qian is currently a Professor at School of Data Science and Engineering, East China Normal University. He received his Ph.D. in computer science from Fudan University in 2004. His research interests include database systems for Internet applications, benchmarking big data management systems, and social media data analytics.


Tea Break


Regular Paper II: Page Table Walk Aware Cache Management for Efficient Big Data Processing

Authors: Eishi Arima, Hiroshi Nakamura
(The University of Tokyo)

Abstract: The performance penalty of page table walks after TLB misses is serious for modern computer systems. Particu- larly, it is more severe while processing big data workloads because they generally experience TLB misses more fre- quently due to larger memory footprint and less access lo- cality. To execute such workloads more efficiently, we need to revisit caches. This is because they are accessed during page table walks to fetch Page Table Entries (PTEs) but not optimized accordingly. Thus, this paper proposes a novel cache management scheme that attempts to optimize the al- locations of PTEs in caches. More specifically, we optimize the eviction priorities for PTEs and data at each level of the cache hierarchy to maximize performance.

Venue Information

BPOE: Westin Xi’an.

Contact Information

Prof. Jianfeng Zhan:
Dr. Gang Lu:      
Mr. Xinhui Tian:


Steering committee:

  • Christos Kozyrakis,   Stanford
  • Xiaofang Zhou, University of Queensland
  • Dhabaleswar K Panda, Ohio State University
  • Aoying Zhou,  East China Normal University
  • Raghunath Nambiar, Cisco
  • Lizy K John,  University of Texas at Austin
  • Xiaoyong Du,  Renmin University of China
  • Ippokratis Pandis,  IBM Almaden Research Center
  • Xueqi Cheng, ICT, Chinese Academy of Sciences
  • Bill Jia, Facebook
  • Lidong Zhou, Microsoft Research Asia
  • H. Peter Hofstee,  IBM Austin Research Laboratory
  • Alexandros Labrinidis,  University of  Pittsburgh
  • Cheng-Zhong Xu, Wayne State University
  • Jianfeng Zhan, ICT, Chinese Academy of Sciences
  • Guang R. Gao, University of Delaware.
  • Yunquan Zhang, ICT, Chinese Academy of Sciences

Program Chairs: 

Prof. Jianfeng Zhan, ICT, Chinese Academy of Sciences and University of Chinese Academy of Sciences
Dr. Gang Lu, Beijing Academy of Frontier Science & Technology
Mr. Xinhui Tian, Institute of Computing Technology, Chinese Academy of Sciences and University of Chinese Academy of Sciences

Web and Publicity Chairs: 
Wanling Gao, ICT, CAS and UCAS

Keynote speaker


Program Committee (Confirmed)

Lei Wang, Institute of computing technology, Chinese Academy of Science
Xu Liu, College of William and Mary
Tilmann Rabl, Technical University of Berlin
Bingsheng He, National University of Singapore
Zhen Jia, Princeton University
Xiaoyi Lu, The Ohio State University

Previous Events





October 7, 2013

IEEE BigData Conference, San Jose, CA


October 31,2013

CCF HPC China, Guilin, China


December 5,2013

CCF Big Data Technology Conference 2013, BeiJing, China


March 1, 2014

ASPLOS 2014, Salt Lake City, Utah, USA


September 5, 2014

VLDB 2014, Hangzhou, Zhejiang Province, China


September 4, 2015

VLDB 2015, Hilton Waikoloa Village, Kohala Coast , Hawai‘i


April 3, 2016

ASPLOS 2016, Atlanta, GA, USA


April 9, 2017

ASPLOS 2017, Xi’an, China